As the number and types of computing devices continue to expand, so does the demand for memory used by such devices. Memory includes volatile memory (e.g. RAM) and non-volatile memory. One popular type of non-volatile memory is flash memory or NAND-type flash. A NAND flash memory array includes rows and columns (strings) of cells. A cell may include a transistor.
During a read operation, an entire row/page of the NAND flash memory array may be read. This may be done by applying a bias voltage to all rows not being read and a reference threshold voltage to the row that should be read. The bias voltage may allow the transistor of the NAND flash memory array to fully conduct. The cells lying on the row being read will conduct only if the threshold voltage is sufficiently high to overcome the trapped charge in the floating gate. A sense amplifier may be connected to each string which measures the current through the string and outputs either a “1” or a “0” depending whether the current passed a certain threshold.
As NAND flash memory cell sizes become smaller, the scaling down of the flash memory cell sizes may cause an increase in the parasitic capacitance coupling between neighboring cells (floating gate transistors) in a flash memory block. This phenomenon, called “inter-cell interference” (ICI), may cause errors in flash memories, leading to degradation in endurance and read performance for NAND flash devices.